1. Technical Field
The present invention relates to a circuit board, and a semiconductor device, which include an inductor.
2. Related Art
FIG. 14 is a view showing a differential amplification circuit disclosed in Japanese Laid-open patent publication NO. 2004-274463. The differential amplification circuit includes: a current-controlled transistor 3; a single pair of active transistors 2a and 2b; a load resistances 1a and 1b; and load inductors 11a and 11b. The sources of active transistors 2a and 2b are connected to the drain of the current-controlled transistor 3, respectively. The load resistances 1a and 1b are connected to the drains of the active transistors 2a and 2b, respectively. One end of the load resistance 1a is connected to the load resistance 1a. One end of the load inductor 11b is connected to the load resistance 1b. The source of the current-controlled transistor 3 is connected to a negative voltage terminal 8. The gate of the current-controlled transistor 3 is fixed to a constant voltage through a current-controlled terminal 6. An input terminal 4a is connected to the gate of the active transistor 2a, and an input terminal 4b is connected to the gate of the active transistor 2b. An input signal in opposite phase is impressed to the input terminals 4a and 4b, and the current passing through the drain is controlled according to the input signal. The other ends of the load inductors 11a and 11b are connected to a positive voltage terminal 7.
Though a phenomenon in which a gain is reduced in a high frequency is caused in such a differential amplification circuit, the gain reduction is prevented by introducing the load inductors 11a and 11b beforehand for increase in the load impedance, wherein the increase is based on use of a phenomenon in which an impedance is increased in a high frequency in load inductors.
In the Japanese Laid-open patent publication NO. H11-340420, there has been disclosed a configuration in which a region for bump connection is provided in an end section located in the center portion of a spiral inductor in a swirling pattern.
In the Japanese Laid-open patent publication NO. 2002-124638, there has been disclosed a semiconductor device with a configuration in which a pad, by which an aluminum interconnect and the external terminals or the like are electrically connected to each other, is formed in a semiconductor integrated circuit, and a high frequency signal passes through the pad. This semiconductor device has a configuration in which a metal coil is integrally formed into the pad in such a way that the metal coil is connected to a parasitic capacity existing between the pad and a semiconductor substrate, which is the base of the semiconductor integrated circuit, in parallel, and the metal coil is located between the pad and the semiconductor substrate; and the parasitic capacity and the coil forms a resonance circuit with a resonance frequency corresponding to the high frequency signal.
In the Japanese Laid-open patent publication NO. H10-335590, there has been disclosed a passive device circuit with a configuration in which thin film capacitors with a high dielectric constant, a spiral inductor, a ground via-hole, and a bonding pad are included, and the two thin film capacitors with a high dielectric constant which are continuously connected to each other, the via hole, and the bonding pad are arranged at the center of the spiral inductor. Here, the bonding pad is an extraction portion of the spiral inductor. All of Japanese Laid-open patent publication NOS. H11-340420, 2002-124638, and H10-335590 have a configuration in which the pad provided in one end of the spiral inductor is arranged at the center of the spiral inductor.
However, a high peaking amount making up for signal attenuation is required because the signal attenuation caused by the parasitic capacity in the circuits is increased when a required operating frequency is high. Thereby, there has been caused a problem that an area occupied by the load inductors 11a and 11b is increased in the semiconductor integrated circuit because the inductances of the load inductors 11a and 11b shown in FIG. 14 are required to be increased.
Moreover, there has been further another problem that the area of the semiconductor integrated circuit is increased because a large number of circuits are formed in the semiconductor integrated circuit, and a large number of load inductors are required when a load inductor is installed into each circuit.